`timescale 1ns/1ns

module Debouncer_test;

reg clk;
reg rst_n;
reg key_in;
wire key_out;

initial begin
    clk = 1'b0;
    rst_n = 1'b1;
    key_in = 1'b1;
    #100 rst_n = 1'b0;
    #110 key_in = 1'b0;
    #1000 key_in  = 1'b1;
end

always #10 clk = ~clk;

Debouncer
#(.clkdiver (20'd20))
dbt
(
    .sys_clk (clk),
    .sys_rst (rst_n),
    .key_in   (key_in),
    .key_out (key_out)
);
    
endmodule